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Title : Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments
Company : DVCon 2011
File Name : 02_2.pdf
Size : 209737
Type : application/pdf
Date : 21-Mar-2011
Downloads : 10

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Featured Paper by Lakshmanan Balasubramanian , Pooja Sundar & Timothy W Fischer

In this paper we propose a methodology to simplify the verification process by creating a library of small, generic Verilog-A (VA) based assertion modules that can be connected together to form more complex checkers for any circuit. This serves as a good infrastructure for designers to easily build their own checkers. A Cadence infrastructure with schematic elements like symbols and forms are built to make the use of the library of assertions for a module level verification more intuitive and user friendly.
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