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Title : Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-off
Company : DVCon 2011
File Name : 06_3.pdf
Size : 119515
Type : application/pdf
Date : 22-Mar-2011
Downloads : 18

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Featured Paper by Chris Schalick

The multi-GHz line rates enabled by SERDES introduce new design challenges in FPGAs, notably signal integrity issues which have given rise to a number of design tools and methodologies. But equally as demanding, if not more so, are the functional verification challenges associated with this complex technology.
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