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Title : Using SystemVerilog Packages in Real Verification Projects
Company : DVCon 2010
File Name : 17_KV166.pdf
Size : 294432
Type : application/pdf
Date : 26-Mar-2011
Downloads : 56

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Featured Paper by Kaiming Ho

This paper details some of the key features and frustrations of using the package construct in SystemVerilog. The package construct is compared to similar features in other languages such as the identically named construct in VHDL and namespaces in C++. Valuable lessons learned over the course of multiple projects in the development of verification environments are described, and the paper makes recommendations for basic DOs and DONTs for SystemVerilog package use. The theme of code reusability is always important, and tips on how packages can be used to achieve this are discussed.
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