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Title : Low Power Verification with UPF: Principle and Practice
Company : DVCon 2010
File Name : 18_PY527.pdf
Size : 380987
Type : application/pdf
Date : 26-Mar-2011
Downloads : 18

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Featured Paper by Jianfeng Liu, Mi-Sook Hong, Bong Hyun Lee, JungYun Choi, HyoSig Won, Kyu-Myung Choi, Harsha Vardhan & Aditya Kher

With the widespread adoption of advanced low power design and implementation techniques in SoC designs, the role of low power verification has been more critical than ever. Advanced low power design techniques, such as power gating, state retention, multi-VDD etc, require significant revisions of the verification methodologies, library infrastructure, advanced CAD tool support and serious engineering efforts to tackle the huge complexity in both implementation and verification.
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