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Title : IEEE 1800-2009 SystemVerilog: Assertion-based Checker Libraries
Company : DVCon 2010
File Name : 31_IN527.pdf
Size : 130509
Type : application/pdf
Date : 26-Mar-2011
Downloads : 27

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Featured Paper by Eduard Cerny, Surrendra Dudani & Dmitry Korchemny

The enhancements to the IEEE SystemVerilog language in the 2009 standard and in particular to the SystemVerilog Assertions (SVA) allow us to create much more useful and versatile checker libraries. They benefit primarily from the following features: checker encapsulation, let declarations, clock and disable inference, deferred assertions, elaboration error tasks, and enhanced property operators. In this paper we first identify the weaknesses of the current checker libraries by examining an example from the OVL library. We then provide a classification of checkers, and show how various forms of effective checker libraries can be created using the new constructs.
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