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Title : Designers Work Less with Quality Formal Equivalence Checking
Company : DVCon 2010
File Name : 15_UP988.pdf
Size : 480760
Type : application/pdf
Date : 26-Mar-2011
Downloads : 3

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Featured Paper by Orly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, & Vadim Ryvchin

Formal Equivalence Checking (FEC) is a technique that formally proves the equivalence of a schematics implementation against a golden RTL model. This equivalence must be guaranteed in light of possible multiple local hand-implemented changes in the schematics. To overcome capacity problems, FEC is usually performed on system sub-blocks, whereas the “environment” is modeled with assumptions written using a property specification language such as SVA. These assumptions must later be proved relative to the driving logic. The majority of FEC tools today are based on SAT-based model checking formal verification engines. In this paper, we describe an approach that can considerably reduce both the time and computational effort required to complete FEC activity in a project. It is based on an additional step introduced to complement the traditional SAT-based model checking algorithm. This step calculates a minimal set of required assumptions using a new SAT-based algorithm. Minimizing the set of assumptions greatly reduces the manual debugging effort required of designers, as well as reduces the number of iterative verifications.
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