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Title : Combining Simulation with Formal Techniques to Reduce the Overall Verification Cycle
Company : DVCon 2010
File Name : 14_SZ917.pdf
Size : 1132243
Type : application/pdf
Date : 26-Mar-2011
Downloads : 8

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Featured Paper by Aneet Agarwal & Gaurav Gupta

With design complexity growing by the day, the need for verification technologies that can complement simulation based verification is also gaining momentum. Formal verification has clearly emerged as one of the strong candidates. In a typical simulation based verification cycle, the number of bugs reported grows exponentially in the beginning, but this number shrinks rapidly thereafter in the cycle and what remains is a few difficult to find corner case issues.
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