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Title : Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions
Company : DVCon 2010
File Name : 32_WV164.pdf
Size : 1336194
Type : application/pdf
Date : 26-Mar-2011
Downloads : 17

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Featured Paper by Doug Smith

Most digital designs inherently possess asynchronous behaviors of some kind. While the SystemVerilog assertion (SVA) language offers some asynchronous controls like disable iff, writing concurrent assertions that accurately describe asynchronous behavior is not so straightforward. SVA properties require a clocking event, making them innately synchronous.
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