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Featured Paper by Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari This paper describes a SystemVerilog transaction-based testbench compliant to the Verification Methodology Manual (VMM). It explains by example the VMM methodology in the creation of a comprehensive constrained-random verification environment using a transaction-based approach. This includes generation of transactions and consumption of them via transactors. The paper also addresses through graphical explanations how VMM macros and classes are used in the makeup of a transaction-based verification testbench. The DUT used for this purpose is a synchronous FIFO model with assertions. The testbench models and results are demonstrated. The complete verification model is available for download.
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