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Featured Paper by Bo Gao Low power and low leakage designs are the new challenges to design and EDA tools today. Low power and low leakage design requires many new design techniques. A low power and low leakage chip design is presented in this paper. This paper will focus on power gating design techniques for cutting down leakage. The power gating is implemented with sleep transistors and voltage islands. In particular, we will describe the methodology to carry out sleep transistor design in a full chip environment. Topics covered by this paper are: creation of voltage islands with sleep transistors, determining the right number of sleep transistors, optimizing sleep transistor placements and optimizing the size of sleep transistors for this low power chip. The results of this power gating design and our experience with JupiterXT/Astro for power gating design will also be presented.
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