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Don’t declare timing closure unless it’s post-SI ! This is a well-known silicon success factor for nanometer designs. Tool like PrimeTime® SI is a well-supported and well-behaved tool for the ASIC world, but to conquer the mixed signal SOC, it’s a little fuzzy and often requires a little extra brain power to drive the custom oriented tools to work the way you want. This paper shares the design and verification experience using PathMill® as the STA engine together with a suite of in-house developed helper scripts (Pathdraw, Pathmeas, Pathsim, Pathogram) to achieve timing closure for the custom designs in a manageable and timely manner, from inner-block, intra-block time budgeting to fullchip level timing analysis flow. In addition to crosstalk performance degradation, power hunger mixed-signal chip induces yet another performance degradation factor due to dynamic IR drop on the power supply rails. The concept of system level simulation which addresses the dynamic IR drop using Nanosim™ is also discussed.
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