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Featured Paper by Brian Slater, Tim Houlihan, Jasmin Mulaosmanovic, Steven Kopec, Jeyenth Vijayaraghavan, Venkat Rao, Sachin Mohan Today’s growing complexity of ICs has necessitated an alternative approach to register modeling and verification. The sheer number of registers proves problematic for manual verification and is prone to human error. In much the same way the overwhelming number of registers burdens the design documentation effort. Changes during any stage of the design cycle result in both verification and documentation rework. This situation necessitates a streamlined process that ties the documentation into the testbench environment, as well as automates register verification. Synopsys’ Register Abstraction Layer (RAL) is a solution that addresses both of these issues. RAL is a testbench register modeling system which enables shadowing and facilitates verification of the entire device register set. It is a subset of the Synopsys’ Reference Verification Methodology (RVM).
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