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Developing a highly integrated SoC ASIC with a PCI Express interface presents many challenges. The process begins with sourcing a high quality PHY core that will work reliably in production and a link layer controller that is compatible with and works seamlessly with the PHY. The next step involves selecting the ideal ASIC technology from a range of options that span Standard Cell, Embedded Array, and Structured ASIC. The proper geometry that will deliver the desired performance is part of this selection criteria.
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