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Developers using FPGAs for the implementation of floating-point DSP functions will recognize one key challenge, namely how to decompose the computation algorithm into sequences of parallel hardware processes with efficient management of dataflow through the parallel pipelines of these processes? We present our experiences exploring architectures with PicoBlazeTM controllers, and a design strategy employing the ESL techniques of model-based and C-based design, to demonstrate how engineers can rapidly integrate highly parameterisable DSP hardware primitives into power efficient high performance implementations in SpartanTM devices.
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