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Verification has become a critical problem with regard to developing today’s high-end digital integrated circuits (ASICs, ASSPs, and SoCs). Advanced devices like these can contain tens or hundreds of millions of logic gates, cost tens of millions of dollars to develop, and take a large engineering team years to design and verify. This paper describes an advanced verification flow from Cadence that is scalable from block- to chip- to system-level designs, and takes the project team all the way from plan to closure. It meets the verification needs of today’s high-capacity, high-complexity designs and the extreme capacity/complexity designs of tomorrow. Using this flow not only injects urgently needed predictability into project schedules (you know where you are, what you’ve done, and what you still have to do) but also increases productivity by optimizing engineering and verification resources. It further increases the quality of the final product while reducing overall project risk.
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