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The electronic design industry continues to push the limits of Moore's Law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that anufacturability issues be addressed much earlier in the design cycle to avoid costly respins and chip failures. Physical and electrical effects at this node challenge both design closure and time to market, and the requirements for design signoff are changing in order to address the inherent manufacturing and process variability. Naturally, this situation can seriously undermine the manufacturability of the design. In fact, a paradigm shift is evident in the all-important signoff analysis step of the digital design cycle.
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