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As semiconductor companies move to more advanced technology nodes, integrated circuit (IC) design teams fi nd more manufacturing effects exerting a larger impact on silicon performance and yield. Designers using traditional methods continue to face signifi cant challenges in reliably meeting yield and performance objectives for current technologies–and will encounter more serious limitations at next-generation technology nodes. New approaches based on fl exible, accurate modeling methods allow engineers to exploit manufacturing knowledge early in the design fl ow to avoid yield problems while fully exploiting more advanced process technologies without themselves becoming experts in the physics of those technologies. Even with relatively recent process technology generations, design teams could expect reasonable silicon yield if they complied with the few hundred rules in typical design rule decks. In turn, companies could count on quickly ramping up production to achieve production yield in new designs comparable to the nominal yield of the production line.
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