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CADENCE ENCOUNTER LOW-POWER DESIGN FLOW More than ever, designers are recognizing the impact of power consumption on IC performance. In every application, power management must take precedence, whether to reduce energy use, or to minimize heat dissipation to lower cooling and packaging costs. Power consumption grows exponentially at 90 nm. Voltage cannot scale indefinitely, and capacitance (dominated by more wires with higher wire capacitance) increases, while frequency keeps going up. Ineffective power management causes decreases battery life, lower chip performance, increases area due to cooling needs, or simply makes the design nonfunctional.
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