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As the complexity, size, and number of custom circuits in SoC designs increase, traditional simulation verification methods are no longer adequate. IC designers are increasingly using formal verification techniques to exhaustively verify that the logic function of the behavioral model and custom circuit are equivalent. In this paper we will discuss the limitations of using standard and symbolic simulation for functional verification, explain the formal verification technique known as equivalence checking, and describe the current methods of functional verification on custom circuits using equivalence checking.
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