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Power consumption has now moved to the forefront of digital integrated circuit (IC) development concerns. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to signifi cant growth in power density. Furthermore, with every new process generation, leakage power consumption increases at an exponential rate. In recent years, a wide variety of techniques have been developed to address the various aspects of the power problem and to meet ever more aggressive power specifi cations. These techniques include clock gating, multi-switching threshold (multi-Vt) transistors, multi-supply multi-voltage (MSMV), substrate biasing, dynamic voltage and frequency scaling (DVFS), and power shut-off (PSO). Figure 1 illustrates the power, timing, and area tradeoffs among the various power management techniques.
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