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“The need to accommodate multiple power domains and multiple voltage levels makes low-power chip design much more complex than normal chip design. Using the Cadence Encounter platform and the ARM Metro IP supporting MSMV design, we were able to quickly validate our low-power design flow and significantly improve our overall lowpower design methodology. Close collaboration with ARM and Cadence expands our design skills and enables us to deliver better performing devices and greater competitive advantage to our customers.”
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