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The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies leads to dramatic increases in mask costs, pushing prototype and low volume production designs to the limit of economic feasibility. Multiple-Project Wafers (MPW), or “shuttle” runs, provide an attractive solution for such designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs of the same technology flow. However, delay cost associated with schedule alignment is ignored in previous work. The savings on mask cost may be easily surpassed by the profit loss due to forced schedule alignment. Therefore, Multi-Flow Multi-Layer Multi-Project Reticles (MFMLMPR) become a more viable mask-cost saving technique for low volume production since mask cost is shared between different layers of the same design and between designs of different technology flows. However, MFMLMPR design introduces complexities not encountered in traditional single-flow or single-layer reticles.
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