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As advanced technologies in wafer manufacturing push patterning processes toward lower-k1 subwavelength printing, lithography for mass production potentially suffers from decreased patterning fidelity. This results in generation of many hotspots, which are actual device patterns with relatively large CD and image errors with respect to on-wafer targets. Hotspots can be formed under a variety of conditions such as the original design being unfriendly to the RET that is applied, unanticipated pattern combinations in rule-based OPC, or inaccuracies in model-based OPC. When these hotspots fall on locations that are critical to the electrical performance of a device, device performance and parametric yield can be significantly degraded. Previous rule-based hotspot detection methods suffer from long runtimes for complicated patterns. Also, the model generation process that captures process variation within simulation-based approaches brings significant overheads in terms of validation, measurement and parameter calibration.
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