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This paper describes the method used in the de-sign of a 26 million transistors chip at BULL to verify the timing performance using the hierarchical timing analysis tool HiTas as well as the interactive path browser Xtas. Those tools have been designed at UPMC and are now commercialized by AVERTEC. The complexity is handled by partitioning the anal-ysis according to the hierarchical partitioning of the design phase. The propagation times within a cir-cuit are represented using a multi-level hierarchical timing view.
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