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Title : Using Static Functional Verification in the Design of a Memory Controller
Company : Averant
Date : 11-Mar-2011
Downloads : 4

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This paper presents a study of verifying a memory controller using a static functional verification tool. Static functional verification is a new technology that does not use vectors or dynamic simulation but analyses the behaviors of a design by the use of a property language. This paper presents the design and verification challenges of a controller, and how static verification was used to debug the design, what improvements were seen in methodology, and what was achieved and learned by using a static tool.
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hi i am functional verification engineer, i want to see the document - praveen - Report As Inappropriate


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