|
This paper describes our experience with the RTL clock gating feature of Synopsys Power Compiler. The chip in question is a specialized microcontroller peripheral ASIC designed for performing real-time control of an internal combustion engine. The design was originally scoped at around 60K gates with a 50mA dynamic current specification. Over the course of the program development, features and capacity were added to the ASIC until the gate count increased to 200K gates. The technology for the design was restricted to a 0.5μm technology due to a 5 V power supply and I/O voltage specification.
|
||||||
|
||||||
|
||||||
