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This white paper describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier’s qualified ASIC design kit and BIST libraries. The methodology describes both a bottom up and a top down approach to SoC design and validation – all at the RTL stage. Application of this approach on real industrial designs indicates enhancement of design productivity and shorter cycle time for functional validation.
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