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Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives. In wired applications, power consumption determines heat generation which in turn drives packaging costs. If not managed properly, this may have significant impact on the end appliance cost. The landscape complicates if we also factor increasing component density of ICs, which leads to progressively increasing power density. The challenge is to pack in more while still consuming less and less power. The breakthrough out of this impasse would be a paradigm shift to build-in power optimization as an integral part of the design process, right from the inception – at the RTL stage. A tool that can advise the designer about power inefficiencies in his programming, avenues through which power can be reduced and mechanisms to implement tried and tested power saving techniques and if possible, even make changes instead of just pointing out errors while coding the RTL itself seems to be the answer. Click here for your copy of the white paper
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