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Title : Avoiding Pitfalls While Specifying Timing Exceptions
Company : Atrenta, Inc.
Date : 17-Sep-2013
Downloads : 68



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In this white paper we will discuss various types of exceptions and describe how to avoid pitfalls using a systematic verification approach. Implementation tools such as synthesis and place and route make use of this information to better optimize the implementation and achieve better area, timing, power or routability. While timing exceptions are potent tool in the hands of implementation engineers, any mistake in specifying them can result in a chip failure.”
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I am looking for evidence to suggest that set_max_delay & set_min_dekay are unecessary. - wasula - Report As Inappropriate

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