|
Advances in silicon technology have enabled unprecedented levels of integration in today's SoC designs. This white paper describes typical issues faced by designers in a typical work-flow for today's SoC designs that includes new block/subsystem RTL development, IP selection and SoC level integration. The paper highlights the need to address implementation issues for the chip project early in the design cycle. The paper then reviews current "rule-checking" approaches and gives an overview of the Atrenta approach to the problem.
|
||||||
|
||||||
|
||||||
