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Design goes through several transformations in a typical RTL-to-layout flow. There are several verification steps in place to make sure that the design intent has not changed. For example, simulation, equivalence checking and so on. In practice, Timing Constraints are created at RTL level just as RTL is created and are refined throughout the design cycle. However, there is no validation step for the constraints prior to their use in the implementation/validation tools, like synthesis, static timing analysis or place & route. Poor constraints impact the chip quality in terms of area, power, and timing. Subsequently, timing closure takes longer. Worst of all, incorrect constraints could result in silicon failing timing and hence a re-spin. There is a critical need for EDA solution to ensure valid timing constraints throughout the design flow. Click here for your copy of the white paper
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