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Design for test (DFT) techniques impose rigorous and generally well-known constraints on a design. These constraints include issues with respect to clock generation and distribution, asynchronous sets and resets, memory controls and tristate busses. In the early design stages, the design focus is on meeting system requirements so it is often the case that DFT issues are not addressed until much later in the process flow. Various products have been developed for DFT checking on post synthesis or gate level netlists but they are specific to particular tools and therefore often lack user specific rules. Even more importantly, these post synthesis techniques do not provide any easy means to update the RTL when DFT changes are required. DFT changes at the gate level, which would have been easy to make had they been flagged earlier, are now much more difficult and may considerably disrupt schedules, design flow and even performance. Often, when schedules are critical, the only feasible alternative has been to sacrifice test completeness. This paper describes how SpyGlass-DFT solves this problem with a look-ahead rule checking method where rules adapt to available information. The look-ahead technique provides test rule feedback to the designer at the RT level, even before many of the test structures are implemented, so that alternatives can be explored and DFT changes can be optimized along with the functional portions of the design. Click here for your copy of the white paper
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