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In real-time simulation it may sometimes be necessary to advance a data sequence {xn} by a given time interval in order to compensate for a delay of the same time interval which occurs somewhere else in the simulation. For example, it is well known that a D to A (digital-to-analog) converter that employs a zero-order hold introduces an effective delay equal to one-half the time step h associated with the data sequence driving the D to A converter. If left uncompensated, this can introduce a significant dynamic error in a closed-loop, real-time simulation. Additional unwanted delays may also occur in the interface used to transfer data between simulation processors, or in data transfers between simulation processors and actual hardware in a hardware-in-the-loop simulation.
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