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We've heard so much about floor planning for integrated circuits – routing, timing awareness, and even leakage and temperature awareness; how often do we come across the term Roof Planning in SoC's? Yet, just as the foundation of any integrated circuit is its substrate, the roof that ensures that the various functional blocks perform as required is its power grid and power delivery system. While much attention has been focused upon the substrate through investigations of substrate noise conduction, little has been done on power grid and power delivery analysis other than the simple exercise of determining i• r drop that is substituted for comprehensive power integrity investigation. As integration continues in accordance with Moore's Law, and nanoscale SoC's include ever more functional blocks operating with switching edge rates of fast fabrication processes capable of multi-GHz operating frequencies, on-chip noise now includes significant L• di/dt content, or dynamic noise, propagated across the chip by the roof above that has two orders of magnitude lower resistivity or impedance as compared with the foundation below. How does one decide what is the girder width of such roofs, optimizing metal usage? How does one determine how best to position the rooms of this integrated mansion so as to minimize total noise? How does one determine how best to place minimal walls of isolating decoupling capacitors so as to protect sensitive rooms from the din created by the entire system? How does one determine how low must the roof be, so as to minimize power consumption that is quadratically (active power) and exponentially (leakage) dependent upon the roof height or the operating supply voltage? This paper details how these challenges may be effectively addressed in SoC floor planning.
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