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A decade ago, the call of the times was for solutions to address the “Power Wall”, at least at leading microprocessor institutions. Conferences discussed looming challenges with supply currents exceeding 1000's of amperes, and temperatures exceeding, what was it, nuclear nozzles, or surfaces of galactic stars, and academia as well as niche industrial efforts rushed after cryogenic or microfluidic cooling systems as well as designs approaching electrical power stations on a chip. Today, power consumption is the single dominant design constraint for integrated circuits, but less noticed, and even less respected is power integrity despite its undeniable role in determining power and energy consumption. Most of us notice that if we dim the lights in our entertainment rooms too much, sharp changes in brightness of our television screens hurt our eyes. Our attempt to reduce lighting energy consumption therefore depends directly upon the level of 'light noise' we encounter. The very same is true for IC's; minimization of energy through supply voltage reduction, the most fundamental approach, depends directly upon power grid noise, or power integrity [1]. As discussed ahead, power integrity is the next dominant challenge, the call of the present for SoC's and SiP's, as power and energy continue to be dominant design constraints.
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