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It is a very rare IC design that does not include some form of on-chip memory, with embedded ROM, RAM, and multi-port register files consuming as much as half the die area. There may be as many as a few hundred unique memory instances on a highly-integrated programmable System-on-Chip (SoC). Some of the most critical paths will start, end or pass through memory instances, and therefore these memory elements must precisely model a comprehensive range of nanometer effects in order to enable the highest integrity SoC verification and subsequent silicon success. Many of the current approaches to memory characterization however are ad-hoc and do not accurately model the detailed timing, noise and power data needed for electrical signoff, forcing re-spins, delaying schedules and increasing the total cost of design. Furthermore, existing memory characterization methods cannot be scaled towards statistical timing (SSTA) model generation. Memory characterization is of increasing concern to SoC designers, who require accurate and efficient models at all stages of design. Compounding this problem are the number and magnitude of the challenges faced. The number of memory instances per chip is increasing rapidly, with some forecasts pointing to greater than 90% of the die area being taken up by memories and other large macros within 5 years. In addition, to support the full range of process, voltage and temperature corners (PVTs) and the sensitivity to process variation, the number of characterization runs and the number of data points per characterization run is growing exponentially.
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