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The rule of thumb in embedded system design has been that adding hardware increases power demands. The careful use of hardware accelerators, however, inverts the rule: adding hardware can reduce power. By analyzing algorithms and implementing appropriate accelerators in programmable logic, developers can increase a design’s performance while reducing power consumption in an embedded computing system. Test results show that accelerators extend trade-off options from as much as 200-fold performance improvement for the same power to the same performance with a 90% power reduction.
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