8.2. Conclusions
 The fundamental limits for lowpower in digital are asymptotic limits and cannot be used in power estimations. Power consumption of digital signal processors is a logarithmic function of signal to noise and depends on technology and the architecture. With better and better energies per transition they will compete in the future with analog processors even for low signal to noise ratios. Power analysis at highest level of abstractions can provide solutions for low power.
 The trend in digital is towards smaller and smaller feature sizes and smaller power supply voltages. This impacts in a negative way analog designs in terms of dynamic range, power, tunability and gain. Only accuracy will benefit from downscaled processes.
 The fundamental limits for lowpower in analog are asymptotic limits. They are combining in one simple equation power, S/N ratios and speed. There are no restrictions regarding voltage swings, circuit topology, noise generated by active circuits, the process constants and linearity. That is why relative comparisons between different designs are difficult to be made based only on the fundamental limits. A designer wants a certain dynamic range and speed with a given accuracy, gain and linearity. Low voltage and low power are imposed by the application and the mixed level context. Starting from general considerations and simple circuits, it is possible to prove that DR*Speed product is limited by power, topology and supply voltage regardless if the circuits are continuous time or sampled data, currentmode or voltage mode. This concept can be generalized for a large class of analog circuits like amplifiers and filters. Scaling down V_{DD} and keeping the same DR*GBW product, power has to increase faster in voltagemode circuits to compensate for power supply down scaling.
 The accuracy requirements give extra boundaries on the minimal power consumption for a given speed, gain and accuracy. This limitation is stronger than the physical limitation imposed by the effect of the thermal noise given the levels of the noise and the levels of the offsets. That is why, in some applications, matching driven power consumption has to be considered.
 In CMOS transconductors, large tunability needed to correct for temperature and process variations gives a significant reduction in voltage swings at low supply voltages and consequently dynamic range reduction. The new technologies optimized for digital applications are impaired by second order effects like velocity saturation and mobility reduction. Most of the concepts used in the past cannot be used anymore. New transconductor concepts which do not rely upon the ideal square law of a MOST, are needed. Another issue is to achieve large tunability without conflicting with the large swing requirement.
 The transconductor from Chapter 4 features a constant input window for all tuning conditions which allows large swings for all tuning situations. This structure overcomes the problems related to nonidealities of the modern MOS transistor in terms of tunability range. The transconductance can be digitally tuned, in ten coarse steps, and continuously, between coarse steps, in the range 30m
A/V¸
85m
A/V. If required, the quality factor can be adjusted such that Gm tuning and Q tuning are independent. Total harmonic distortion stays below 50dB for input amplitudes of 1.8Vpp in all tuning conditions and well below 60dB for amplitudes lower than 1Vpp. Large swing property yields a large dynamic range over power ratio. In worst case the noise excess factor is close to 6 and power dissipation is 1.48mW from 3.3V supply. The transconductor can be used as a GmC integrator for filter applications.
 Positive feedback is a promising technique for enhancing gain in submicron CMOS because current matching in modern technologies improves. It avoids cascoding for having large gains and can be used for lowvoltage applications. The second type of integrator considered in this chapter is a current GmC integrator with local positive feedback for enhancing the gain. The reason for using this integrator consists in the lowvoltage, high linearity and very high frequency of operation with a high power efficiency. It is compatible with standard digital technology has a high quality factor Q and can work down to 1.5V power supply voltage. By using the DR*Speed concept from Chapter 3 it is shown that the current GmC approach has better power figures for the same working conditions than OTAC approach.
 The two integrators from Chapter 4 are used to realize the video filter from Chapter2 in an analog way and to make a comparison in power to the digital approach. It turns out that digital approach has less power consumption per pole than the analog counterparts for a 0.5mm CMOS process. This explains why, in the future, digital filters will be used even for low DR applications.
 There are filter applications where matching requirements and noise requirements have the same importance, with constraints on power consumption and linearity. Channel selectivity in receivers has been realized until recently using SAW filters. Those components are external components and therefore integration on chip of selectivity has become a major concern in receivers. From Chapter 3 we already know that selectivity increases the noise power and requires extra power consumption to achieve it. In a polyphase filter, selectivity is ensured by using polyphase signals without the need of bandpass sections. They can discriminate between positive and negative frequencies and therefore, using this property, selectivity can be achieved. By using a low power integrator, we have shown how to realize a polyphase filter needed for image rejection in a mobile transceiver. The filter has a central frequency of 1MHz, a gaussian to 6dB transfer and a passband from 500KHz up to 1.5MHz. The filter has been simulated in a 0.35mm CMOS technology with a supply voltage of 2.5V. The image rejection can be made better than 52dB with a power consumption of 15mW with a dynamic range of 69dB. When compared to activeRC realizations with opamps it shows power figures better with a factor six. The gaussian transfer allows good time response as required in data transmission.
 Chopping is the only method which reduces 1/f noise and offset without modifying the baseband white noise. As a modulation method, it boosts the dynamic range and accuracy of analog circuits without power penalty. Although, chopping is a low frequency technique, there are applications where bandwidths of the signals are in the MHz range. We have introduced a new method to use chopper modulation at high frequencies and a lowvoltage, lowpower, chopped transconductance amplifier for mixed analogue digital applications was presented. This OTA is meant for highend applications. Chopping and dynamic element matching allow low noise and low residual offsets up to 1MHz. The sensitivity to substrate noise is tackled in the design. Experimental results show residual offsets of less than 370m
V up to 1MHz chopping frequency. Second order effects like charge injection and residual offsets are discussed. By chopping, the S/N is improved with about 6dB which brings a factor 4 reduction in power.
 In mixed level applications accurate voltage references are difficult to realize due to the lack of well characterized lateral pnp’s and the large offsets inherent to CMOS opamps. Another problem tackled is related to the realization of an accurate bandgap voltage reference in CMOS. It is shown that by using chopping techniques and a chopped OTA, the accuracy of a bandgap voltage reference can be improved about ten times without laser trimming and with the benefit of reducing the 1/f noise of the amplifier. The bandgap referenced voltage has a spread of 3.2mV after chopping and 7.5mV power consumption.
 The chopped amplifiers presented further are primarily meant as amplifiers capable of driving headphones in portable digital audio. The generality of the method makes them suited for a large class of designs. In audio applications, extra offsets give extra dissipation in the headphone. It is also desired to have high linearity and low noise for all possible loads. That is why chopping can be used to improve the accuracy and the dynamic range. The first amplifier has been realized in a 0.8mm CMOS. Measurements show a dynamic range of 111dB for the amplifier configured as a follower when chopping at 1MHz. For high ohmic loads, the linearity is better than 91dB for 1.5V voltage swing. For low ohmic loads, the THD is better than 83dB. The power consumption is 1.8mW from a 3.3V power supply. The class AB control circuit of the output stage is limiting the lowest value of the supply voltage at about 1.8V.
 The second amplifier designed in 0.5mm CMOS technology has a new class AB output stage which can work at lower supply voltages. The open loop gain of this amplifier has been increased to 92dB by using gain boosting techniques. Offset simulations show a static offset of 1.67mV. Chopping at 10MHz, the simulated residual offset is 450m
V but at 1KHz chopping, the simulated residual offset is 10m
V. The linearity of the opamp is better than 85dB for signal amplitudes close to 2.4V_{pp}. The power consumption of the opamp is 1.5mW from a 3.3V power supply voltage being dominated by the power consumption of the class AB output stage. It can work down to 1.4V with reduced swing and dynamic range.
 The last example is a D/A interface with Sinc approximated semidigital reconstruction filter. It shows that lowpower techniques at the highest level of abstraction can lead to power savings which cannot be obtained unless the complete system is taken into study. By using Sinc approximation in the frequency domain and an iterative procedure one can reduce the number of coefficients taking into account process tolerances such that the out of band rejection of noise requirement is met. Compared to the standard solutions we have reduced about four times the number of the coefficients for the same requirements. With only 25 coefficients we get more than 50dB stopband rejection of the out of band noise. The resolution of the system is impaired by circuit nonidealities such as component noise, mismatches, device nonlinearities, substrate bounce and clock jitter. To increase the matching in the differential FIR filter, a floating mirror has been used. The differential opamp with commonmode control can be chopped or unchopped depending on the resolution required. The D/A interface has been realized on chip in a 0.8mm CMOS, 5V technology. Measurements shows a THD of 86dB and a noise floor at the output close to 120dB.
 The Sinc approximation in the time domain provides a solution to decrease power in the digital part of the D/A interface without increasing power consumption in analog. By using this method the best partitioning of the system in terms of power can be found. Accordingly, power consumption in the digital domain can be reduced. By using a combination of the two methods namely Sinc approximation in time domain or Sinc approximation in digital domain, it is shown that keeping the same complexity of the FIR filter as in standard approach, a reduction in power in the digital section, with a factor four is possible.
