A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter

Prev TOC Next

7.6. Noise properties of the D/A interface

The semidigital FIR filter and the low pass analog filter will increase the amount of noise at the output. Another source of noise is the clock jitter. We are considering here only the noise of the current sources and the clock jitter. The opamp noise can be easily quantified. As long as the effect of the noise generated in the analog part of the D/A converter is larger than the quantization noise, the resolution of the converter will be impaired. One should be able to quantify those effects and to design a low noise analog interface.

Fig.7.16: Noise generated at the output

In fig.7.16 the realization of the coefficient a i has been considered. Due to the differential approach, the current sources Ii are both present when the coefficient a i is active and gives a contribution to the output. The white and 1/f noise from the cascode transistors can be neglected. The noise sources which give a significant contribution at the output are shown explicitly.

7.6.1 White noise considerations

The effect of this noise at the output can be considered when the input PDM signal represents a pure sinusoidal waveform represented with ones and zeros with a density p and 1-p respectively. During the period Ts, the coefficient a i is active and the current Ii+noise flows in the parallel connection R and C. Because the signal is periodic, the switch will be on and off periodically. The noise transfer to the output, differs for pMOS and nMOS current sources as:



In the noise transfer appears the transconductance of the transistor configured as a current source and the pole determined by the RC combination in the low pass filter. The power of the output white noise due to the current Ii during the interval Ts can be determined from the noise bandwidth of the circuit and the power spectral density of the voltage noise V2nip and V2nin respectively:


Denote fsig=1/Tsig the audioband from 0 to 20KHz. From fig.7.16 we can find the relationship between the oversampling ratio OR=fs/2fsig in the converter and the interval t:


During this interval, the current Ii can be dumped to the ground or can be used to make larger swing in the differential approach. The noise and the current Ii are available only a fraction (1-t) from the total Tsig. The noise has to be considered in the audioband. Therefore, the power of the noise available at the output in the interval Tsig will be:


The pulse shown in fig.7.16 is not a singular pulse and will appear in the interval Tsig according to the density of ones in the representation of the sinusoidal signal in this interval. Given the fact that the density of ones and zeros is p and 1-p respectively and the number of total samples is Q, the total noise generated by the pMOST and nMOST current sources due to the coefficient ai in the Tsig becomes:


The total noise can be found by adding all the individual noise contributions of the coefficients ai in the interval Tsig:


The current Ii is a fraction of the total current needed to bias the FIR filter Ii=aiITOT. Now, the transconductances gmi,p and gmi,n can be replaced by:


where VGTin,p are the effective gate-source voltages for the pMOS and nMOS branches. The voltages VGTi are all equal in the case of pMOS and nMOS current sources respectively. In the FIR semidigital filter, the sum of the coefficients Sai is one. Hence, we can find a relationship between the total current ITOT ,the density of ones and zeros in the representation of the signal, the oversampling ratio, the effective gate-source voltages and the total power spectral density of the noise voltage at the output.


As a conclusion, in order to minimize the white noise present at the output of the converter one has to increase the oversampling ratio and to decrease the total current ITOT in the semidigital filter. Decreasing the value of the resistor R will give a negligible influence of the resistor noise at the output. On the other hand, the output stage of the opamp is rail to rail to ensure large swings of the signal. If the common mode voltage at the input of the opamp is VDD/2, then VDD=2ITOTR in order to use the full swing at the output. In the particular case p=1/2 the density of ones and zeros in the signal representation are equal. Under this assumption and by denoting:


then the power spectral density at the output becomes:


7.6.2 1/f noise considerations

In the following paragraph we are considering the effects of the 1/f noise on the power spectral density of the output noise voltage. The noise transfer to the output has the same behaviour as the white noise transfer from (7.31) and (7.32). Given the power spectral density of the 1/f noise present at the gates of the pMOS and nMOS current sources of the coefficient ai:


one can find the output noise power up to the corner frequency of the 1/f noise fc. It can be approximated as follows:


This noise is present at the output only during the period Ts and should be weighted with the density of ones and/or zeros. By following the same pattern as in the case of the white noise, we can find the total noise power at the output as a function of oversampling ratio, signal statistics and the FIR filter structure:


The transconductances of the PMOS and NMOS transistors depend on the coefficient ai and the total current needed to bias the semidigital filter as:


All the transistors of the current sources have the same length Lp and Ln respectively and different widths according to the filter coefficients. By using the property of the filter coefficients Sai=1 it is possible to rewrite (7.35) in the following form:


The total noise coming only from the semidigital FIR filter can be found by adding the contributions of the white noise and the 1/f noise. Besides, we have to take into account the noise of the opamp and the noise generated by the feedback resistor R.

7.6.3 Noise generated by the clock jitter

Another contribution upon the total noise generated by the D/A interface would be the noise generated by the clock jitter. As long as the FIR semidigital filter is being implemented with a lot of coefficients, the area would be large and the clock distribution would be a problem. Going to high oversampling ratios OR, to be able to increase the accuracy of the converter we encounter the clock jitter and its consequences. The clock jitter can be reduced by using a crystal referenced clock. In order to consider those effects we have to take into account two possible realizations of the PDM codes, non return to zero (NRZ) and return to zero (RTZ) coding.

a. NRZ coding

Let’s assume an uncertainty Dt in the sampling moments of the clock. In the case of NRZ coding, the actual values of the output depend on the previous values generating inter-symbol interference. In fig. 7.17.a, the currents flowing in the resistor R are shown. The uncertainty Dt in the sampling moments kT will generate an uncertainty DV in the low-pass filtered voltage at the output of the D/A. The output voltage VO in the period [kT,(k+1)T] according to fig.7.17. b) and the time constant of the low-pass filter is:


From (7.38) it is obvious that NRZ coding generates inter-symbol interference because of the correlation between samples. If the period of the signal PDM represented is Tsig , the period of the top samples T, and the number of samples Q, then the average of the output voltage VO(t) can be approximated as:


Fig.7.17: NRZ coding

The assumption would be that the low-pass filter has a larger time constant RC compared to the period of the top samples T. In order to find the effect of jitter on the output noise, consider (7.38) for t=(k+1)T under the assumption RC>>T:


The consequence of jitter will be the spread of the mean value of the voltage variation considered in (7.40). The mean value of this variation in the interval Tsig is:


and its spread as a function of the clock jitter :


This value represents actually the rms noise in a bandwidth 1/Tsig.

b. RTZ coding

Fig.7.18 illustrates the return to zero current top pulses and the output voltage VO(t) exaggeratedly small for understanding purposes. In the case of return to zero, the top current pulses will go periodically to zero and the inter-symbol interference will be reduced. This has consequences on signal dependent distortion too. However, we have to face another problem inherent to return to zero coding. Because current steps are larger now in comparison to NRZ coding, the errors made in the area of the top pulses by clock jitter are also larger, generating larger noise at the output.

Figure 7.18: RTZ coding and jitter

The period of the output signal VO(t) is denoted Tsig. The effect of the jitter on the output voltage has to be considered in a bandwidth given by 1/Tsig following the same pattern as in the case of noise calculation at the output. The average of the current top pulse IR[kT] in the period T is:


The mean of the output voltage VO in the interval [kT,(k+1)T] depends on the current IR[kT]:


Clock jitter generates the spread of the Ton denoted sTon which gives the spread of the output voltage VO denoted sVO. The relationship between s2Ton and s2VO is given by:


This represents the power of the noise related to the bandwidth 1/T which has to be related now to the bandwidth 1/Tsig. The power of the noise in this bandwidth will be:


The interval in which the pulse is ON denoted Ton is related to T as Ton=l T. By using the oversampling ratio OR=Tsig/2T, the duty cycle l and (7.46), the power of the noise in bandwidth 1/Tsig is found to be:


The signal to noise ratio in the bandwidth 1/Tsig when only the clock jitter is taken in consideration can be determined from:


The area of the top pulse will be larger when Ton increases and the noise generated by jitter will have less influence on the total S/N. As a conclusion, the larger the ON time of the pulse, the better the S/N and larger clock jitter can be tolerated. When return to zero coding is being used the inter-symbol interference will become less dominant as in the case of non return to zero coding. Breaking the correlation between the current top pulses, the signal dependent distortion will be improved.

As a final example, consider 1/T=2.8MHz, OR=64 and l =3/4. A clock jitter of sTON=100ps gives a S/N ratio of about 91dB corresponding to 15 bits resolution. In order to have a higher resolution than 15 bits a clock jitter of about 50ps or less will be required. This gives a design condition for the clock generation part of the interface.

Fig.7.19: Circuit diagram


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Reverie: All That Glitters is not Past
More Editorial  
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
Digital and FPGA Hardware Designer for Giga-tronics Incorporated at San Ramon, CA
SoC Design Engineer for Intel at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
DesignCon 2017 at Santa Clara Convention Center Santa Clara CA - Jan 31 - 2, 2017
IPC/Apex Expo 2017 at San Diego Convention Center San Diego CA - Feb 14 - 16, 2017
DVCon 2017 Conference at DoubleTree Hotel San Jose CA - Feb 27 - 2, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy