CHAPTER 5

Chopping: a technique for noise and offset reduction


Prev TOC Next

5.8. Conclusions

From Chapter 3 we came to the conclusion that high accuracy and large dynamic range will cost power. In the following chapter different methods to reduce 1/f noise and offset are being discussed. These methods are based on sampling and modulation and their advantages and disadvantages are reviewed. Chopping is the only method which reduces 1/f noise and offset without modifying or at least without increasing the baseband white noise. Although, chopping is a low frequency technique, there are applications where bandwidths of the signals are in the MHz range. Here, the residual offsets generated from charge injection will limit the chopping frequency.

A method to use chopper modulation at high frequencies is introduced and a low-voltage, low-power, chopped transconductance amplifier for mixed analogue digital applications has been presented. This OTA is meant for high-end applications. Chopping and dynamic element matching allow low noise and low residual offsets up to 1MHz. The sensitivity to substrate noise is tackled in the design. Experimental results show residual offsets of less than 370m V up to 1MHz chopping frequency. Second order effects like charge injection and residual offsets are discussed. By chopping, the S/N is improved with about 6dB which brings a factor 4 reduction in power.

In mixed level applications accurate voltage references are difficult to realize due to the lack of well characterized lateral pnp’s and the large offsets inherent to CMOS opamps. Another problem tackled in this chapter is related to the realization of an accurate bandgap voltage reference in CMOS. It is shown that by using chopping techniques and a chopped OTA, the accuracy of a bandgap voltage reference can be improved about ten times without laser trimming and with the benefit of reducing the 1/f noise of the amplifier. This example shows that low power is a relative term which has to be adapted to the application.

CST: Webinar

Aldec Simulator Evaluate Now

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
The Future: EDA Hiring faces Headwinds
Peggy AycinenaIP Showcase
by Peggy Aycinena
Happy Talk: CEOs, Celebrity, Seasoning
More Editorial  
Jobs
DSP Tools Engineer for Cirrus Logic, Inc. at Austin, TX
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
Design Verification Engineer for intersil at Morrisville, NC
RF IC Design Engineering Manager for Intel at Santa Clara, CA
Upcoming Events
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
IPC APEX EXPO 2018 at San Diego Convention Center San Diego CA - Feb 24 - 1, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise