CHAPTER 2

Power considerations in sub-micron digital CMOS


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REFERENCES

[1] R.W. Keyes, "Physical limits in digital electronics", Proceedings of the IEEE, vol.63, no.5, pp.740-766.

[2] J.D. Meindl, "Theoretical, practical and analogical limits in ULSI", IEEE IEDM, Technical Digest, pp. 8-13, 1983.

[3] J.D. Meindl, " The evolution of Solid State Circuits: 1958-1992-20??", 1993, IEEE ISSCC Commemorative Supplement, pp.23-26, Feb. 1993.

[4] F.W. Sears, "Thermodynamics", Addison Wesley, Reading, Mass. 1953

[5] H. Haken and H.C. Wulf, Atomic and Quantum Physics, Springer Verlag, pp.83-85, 1984

[6] E.A.Vittoz, "Low-power design: ways to approach the limits", in IEEE International Solid-State Circuits Conference, Dig. Paper, 1994, pp.14-18

[7] E.A.Vittoz, "Future of analog in the VLSI environment", in Proc. IEEE ISCAS, pp.1372-1375, 1990

[8] Semiconductor Industry Association, "The National Technology Roadmap for

Semiconductors" 1997, pp. 46-47.

[9] J.A.J. Leijten, J.L. Meerbergen and J. Van Jess, "Analysis and reduction of glitches in synchronous networks", Proceedings ED&TC, pp.398-403, 1995

[10] T. Sakuta, W. Lee and P. Balsara, "Delay Ballanced multipliers for low power, low voltage DSP core", 1995 Symp. on low power electronics, Dig. Tech. Papers, pp. 36-37, 1995

[11] A.R. Chandrakasan and R.W. Brodersen, " Low power digital CMOS design", Kluwer Academic Publishers, Norwell MA, 02061 USA and Dordrecht, The Netherlands, ISBN 0-7923-9576-X.

[12] A. Bellaouar and M.I. Elmasry, "Low power digital VLSI design: Circuits and systems", Kluwer Academic Publishers, Norwell MA, 02061 USA and Doordrecht, The Netherlands, ISBN 0-7923-9587-5.

[13] A.W.M. van den Enden, N.A.M. Verhoeckx, Discrete-time signal processing: An introduction, pp. 173-177, Prentice Hall, 1989, ISBN 0-13-216755-7.

[14] D.J. Kinniment, J.D. Garside and B. Gao, " A comparison of power consumption in some CMOS adder circuits", Proceedings of PATMOS, Eds. C. Piguet, W. Nebel, pp. 119-132, ISBN 3-8142-0526-X.

[15] J. Smit, "On the energy complexity of algorithms realized in CMOS", in Proceedings of the ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Mierlo, The Netherlands, Nov. 1996, pp.331-341.

[16] Enrico Macii, "Low power design in deep submicron electronics", ISBN 0-7923-4569-X, pp.363-364

[17] H.J.M. Veendrick, "Short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits", IEEE Journal of Solid-State Circuits, vol. SC-19, pp.468-473, Aug. 1984.

[18] R.M. Swanson and J.D. Meindl, "Ion-implanted complementary MOS transistors in low-voltage circuits", IEEE Journal of Solid-State Circuits, vol.SC-7, no.2, pp.146-152, April 1972.

 

 

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