Power considerations in sub-micron digital CMOS
2.6. Ways to low-power in digital
We have discussed so far power issues related to the architecture level. For every level of abstraction from fig.2.1 there are ways to reduce power which have an influence on analog functionality integrated on the same chip. In this section, we are going to point out which are the most important ways to reduce power at different levels and the consequences on analog functions ,  and .
2.6.1. Process technology
The most effective way to reduce power at device level is to reduce the power supply voltage. This has consequences on the delay as power supply voltage approaches the threshold voltage. The problems we want to improve are:
Analog will benefit also from this except for supply voltage reduction.
2.6.2. Logic and circuit level
There are many techniques available for minimizing power at this level like:
2.6.3. Power reduction at architecture level
At the architectural level of abstraction there are possible certain techniques for power reduction like:
2.6.4. The algorithmic level
To reduce power at the algorithm level one should be able to optimally use an algorithm such that:
2.6.5. Power at system level
At this level of abstraction a good partitioning of the system in terms of digital or analog solutions is important. Examples of methods for power reduction are:
Since the average energy dissipation per cycle is proportional to CV2, where C is the load capacitance and V is the voltage swing, the obvious path to minimum power is to reduce C by scaling down minimum feature-size and especially to reduce V (see also ). Voltage scaling represents an efficient way to reduce power in digital. The minimum allowable value of supply voltage VDD for a static CMOS inverter was derived by R. Swanson  as:
The condition arises from the requirement to have voltage gains larger than one. However, reducing the supply voltage down to that value has other consequences. The well known power-delay product or energy per transition, is proportional to VDD2. For a simple inverter, when VDD is down-scaled close to VTn+½ VTp½ there is a speed penalty to be paid. The simple inverter shown in fig.2.12 has a delay given by:
The lower the supply voltage the higher the delay. Therefore, we have to operate the circuit at the slowest possible speed. In order to maintain the throughput it is necessary to compensate for the increase of the delay by sizing-up W/L ratios of the transistors. When sizing-up the W/L of the transistors, the drain and source diffusion increases and the parasitic capacitances are increasing giving the possibility for an optimum in terms of scaling for keeping the delay constant.