CHAPTER 2

Power considerations in sub-micron digital CMOS


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2.4. S/N ratio and power in fixed point applications

In section 2.3 the relationship between power consumption and S/N has been discussed. The assumption in eq. (2.12) is that quantization noise comes from only one noise source. In practical situations this is however not true. When processing with a fixed number of bits quantization will occur to prevent the increase of number of bits after multiplication. The limitation of the word lengths of intermediate results has one of the most complicated consequences on digital filters. An intermediate result appears as an outcome of a multiplication and/or addition.

We shall assume here that we want a B bit system in which the quantities are represented as B-bits words in a fixed-point representation with one sign bit before the decimal point. A product requires 2B-1 bits while an addition requires only B+1 bits. The addition increases the number of bits before the decimal point and the multiplication needs an increased number of bits after the decimal point. Addition introduces overflow problems and multiplication quantization problems. The problem of overflow can be solved by scaling the signal before the filter. Because every multiplication produces an increased number of bits, we have to use quantization after every multiplication in applications with fix number of bits and, therefore, we are introducing noise again. The number of bits used strongly affects all key parameters of a design, including speed, area and power. That is why it is desirable to minimize the number of bits.

To find a relation between power, signal to noise ratio S/N and the type of the architecture, we have to compute the S/N in the case of FIR and IIR architectures. Given the quantization step q, the noise power of the quantization noise Pe=q2/12 and the gain factor k for avoiding overflow, we can consider that the signal power at the input provided by the A/D converter is [13]:

(2.15)

The power of the signal in the output can be computed for every possible architecture by knowing the transfer function and the input signal power. As explained, after multiplication quantization occurs and the noise power at the output increases. The method to find the relationship between computational power and S/N is presented in Appendix 1 where, the case of FIR and IIR2 structures has been considered. Given the number of operations per clock cycle, the energy per transition, the desired transfer function and the number of coefficients, one can find the relationship between power and S/N taking into account the noise sources in a FIR or IIR2 structure. In eq.(2.16) the number of operations per clock cycle and the energy per transition are included in the constant kmult while the desired transfer function is included in term WFIR.

(2.16)

The same type of logarithmic relationship holds for an IIR2 structure between the computational power and signal to noise ratio S/N.

(2.17)

 True Circuits: Ultra PLL

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