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1.1. Motivation

From a historical point of view, VLSI designers have used the speed as a performance figure in comparing different designs [1], [2]. In terms of area and performance, a lot has been gained from scaling down the CMOS process towards smaller feature sizes [3], [4], [5]. The main concern in the late eighties was to find the best trade-off between performance and area where power consumption was not a design criterion but a subsidiary item. A significant change in the attitude of the designers is the desire to have remote access to computation capabilities without the need to be connected to the wired power supply. Here, the major concern is the weight and size of batteries which depends on the amount of power dissipated by the circuits. The largest majority of portable electronics use rechargeable batteries where the improvement in energy density will be only 40% at the end of this century. Given the slow improvement in the energy capacity, low-power design techniques are essential for portable devices. Subsequently, the efforts of researchers were directed towards power estimation and power reduction techniques [6], [7], [8].

In non-portable applications power consumption it is of concern since the cheap plastic packages for large volume market can withstand only 1W power dissipation. The trend is to increase the integration on chip of digital and analog functionality in more complex systems. In the past, large packages and/or cooling fans were capable of dissipating the heat generated on chip. As the density of integrated systems on chip increases, the cooling method will limit the complexity of those systems. A simple example is the increase of the clock rate of microprocessors (up to 600MHz) in order to increase the amount of computations per time unit. In those applications a figure of merit is the amount of processing per unit of power dissipation (e.g. MIPS/Watt). The power of microprocessors has increased up to some 30W in the last years which generate the situation where personal computers in US use some 10% of the commercial electricity consumption which accounts for the indirect production of CO2 from 5 million cars. That is why environmental incentives have required green

chips [9].

The traditional low-power, low-throughput applications were pocket calculators, wristwatches, hearing aids and pacemakers. However there are a large number of new applications requiring low-power but high throughput [10]. Emerging portable applications are smart cards, DVD players, GPS navigators, digital cameras and camcorders. The advent of portable communications systems like digital cellular telephony networks which employs complex speech algorithms and radio modems, demand lower and lower power. In personal communication systems (PCS) voice, data and full-motion digital video will be transmitted wireless or wire-bound by using portable multimedia access [11]. Obviously, largely increased capabilities must be incorporated in the portable environment capable to support multimedia capabilities. The portable phones are dominating the future applications by far. Low power is the key issue in all those applications and has become the major concern.

The mobile communications equipment market is the fastest growing market today. Cellular phones, cordless phones, paging receivers and mobile IT devices (PDA, Palm Top Computers) are becoming high tech due to ever increasing digital services. The analogue trend in those applications is towards low cost while new digital technologies are emerging. The trend is to increase the frequency and the amount of processing per unit of power dissipation (MIPS/power) at higher integration of functionality. In traditional applications and new emerging applications as well, CMOS will dominate by far while the tendency is to go to higher frequency, lower supply voltages and to higher integration of functionality with better computation power [12]. In conclusion, power is becoming a major concern in portable but also in wired power supply applications.

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