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A - B - C - D - E - F - G - H - I - J - K - L - M - N - O - P - Q - R - S - T - U - V - W - X - Y - Z
Index

An index of topics in this book

Symbols

@ISA, 1

A

Accellera, 1
ADA programming language, 1
Analyzing and optimizing the test suite, 1
Automated test generation, 1
Automatic regression suite ordering, 1

B

BASIC programming language, 1
Basic sub-condition coverage, 1
Batch mode operation, 1
Behavior
expected, 1
prohibited, 1
Behavioural level description, 1
Best practices, 1
BFMs
bus functional models, 1, 2
Black box testing, 1
Block coverage, 1
Branch coverage, 1
calculation of, 1

C

C programming language, 1
Closed box testing, 1
Code
results filtering, 1
Code checking
worked examples, 1
Code coverage
and project management, 1
as a quality control parameter, 1
as a verification advisor, 1
at gate level, 1
at the behavioral level, 1
in the design flow, 1
measurements and targets, 1
of state machines, 1
origins, 1
practical guidelines, 1
RTL, 1
transient behavior, 1
Code coverage tools
capabilities, 1
operation, 1
Coding rules, 1
Collecting simulation results, 1
Command line
batch file, 1, 2, 3, 4
Command line operation, 1
Compare test benches, 1
Concurrency, 1
Condition and Expression Coverage, 1
Cores, 1
Coverage
sign-off, 1
Coverage analysis tools, 1
Coverage directed verification, 1
using properties, 1
Coverage metrics, 1
filtering, 1
FSM arc, 1
FSM cycle information, 1
FSM path, 1
FSM state, 1

D

Dealing with information overload, 1
Deglitching, 1, 2
Design abstraction, 1
Design capture, 1
Design changes, 1
Design flow, 1
Design partitioning, 1
Design rule checker, 1
Design rule checkers, 1
Design rules
attributes, 1
coding, 1
databases of, 1
documentation, 1
examples, 1
naming, 1
style, 1
Design specification, 1
Design steps, 1
Device Under Test, 1, 2
Directed expression coverage, 1
Documentation rules, 1
Duplicate tests, 1
DUT, 1, 2
Dynamic property checking, 1, 2

E

ECO
engineering change orders, 1
Editors
graphical, 1
text, 1
Exclude code, 1, 2
Expected behavior, 1
Exponential growth in testing time, 1
Expression Coverage, 1

F

Fault simulation, 1, 2
FEC, 1
Filtered code
at different levels in a hierarchy, 1
identifying, 1
information about, 1
Focused Expression Coverage, 1, 2
FSM, 1
coverage, 1
cycle, 1
link, 1
path coverage, 1
path reachability, 1
supercycle, 1
FSM results summary, 1
Functional coverage, 1
Functional testing, 1

G

Gate level descriptions, 1
Gate level testing, 1
Graphical editors, 1

H

Handling design changes, 1
Hardware design tools, 1
HDL capture tools, 1
HDL Verification
the verification gap, 1
why do it?, 1, 2, 3
Hierarchy browser, 1

I

Information overload, 1
handling, 1
Instrumenting, 1
Intellectual property, 1
Intelligent
bus functional models, 1
bus protocol monitors, 1
test controller and data checker, 1
IP, 1

J

JTAG, 1

L

Linters, 1

M

Manual path extraction, 1
Merging results, 1
ModelSim simulator
evaluation copy, 1
Multiple conditions, 1
Multiple sub-condition, 1
Multiple test benches, 1
merging results, 1

N

Naming rules, 1
Netlists, 1
Newsgroups, 1

O

Observability, 1
Open box testing, 1
OpenMORE, 1
Operation
batch mode, 1
command line, 1
Optimizing test benches, 1

P

Parameter file, 1
Pascal programming language, 1
Path coverage, 1
Pattern matching, 1
Perl
greedy quantifier, 1
lazy quantifier, 1
programming language, 1
regular expression, 1
scripting language, 1
Portability, 1, 2
Post-simulation results filtering, 1
Pre-silicon validation, 1
Probe, 1
Prohibited behavior, 1
Properties, 1
expected behavior, 1
prohibited behavior, 1
Property
definition files, 1, 2

Q

Quality control, 1

R

Reachability based path extraction, 1
Redundant tests, 1, 2
Register Transfer Level description, 1
Regression suite ordering, 1
Regression testing, 1, 2
Results
presenting, 1
Results filtering
after simulation, 1
Reusing the test environment, 1
RMM, 1, 2
RTL, 1
Rule checker
results viewing, 1
using, 1
Rules databases, 1

S

Self-checking test benches, 1
Signal toggle coverage, 1
Signal trace file, 1
Signal tracing coverage, 1
Signals file, 1
Simulation bottlenecks, 1
Simulation time
minimizing, 1
SoC, 1
Source code
analysis, 1
State Machines
deglitching, 1, 2
State Navigator, 1
Statement coverage, 1
Structural testing, 1, 2
Style rules, 1
Subsets, 1
Supercycle, 1
Superfluous code
results filtering, 1
Supported simulators, 1
Synthesis, 1
System on a chip, 1

T

Tabular trace file, 1
Tabular tracing, 1
TAP, 1
controller, 1, 2, 3, 4, 5
Test bench, 1
construction, 1, 2, 3, 4
coverage directed, 1
overlap, 1
responses, 1, 2
self-checking, 1
stimulus, 1, 2
Test benches
comparing, 1
for ECOs, 1
optimizing, 1
Test plan, 1
Test suites, 1
optimizing, 1, 2, 3
Testing time
exponential growth, 1
Text editors, 1
Toggle coverage, 1, 2, 3
Transition coverage, 1
Triggering coverage, 1

U

Unexecutable code
results filtering, 1
Unreachable code
results filtering, 1

V

Variable trace coverage, 1
Verification flow, 1
Verification Navigator, 1
evaluation copy, 1
Visual checking, 1
VN-check design rule checker, 1, 2
evaluation copy, 1
VN-Property DX, 1, 2

W

Web sites, 1
White box testing, 1
Wildcards, 1

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