Hard IP, an introduction
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5 SPECIAL CHALLENGES AND OPPORTUNITIES WITH HARD IP
5.1 Retargeting Analog and Mixed Signal Designs
5.1.1 Layout Considerations for Analog
5.1.2 Can Analog Designs be Successfully Migrated?
5.1.3 A Practical View of Analog Migration
5.2 Hierarchy in Hard IP Migration
5.2.1 Hierarchy Maintenance in Layouts
5.2.2 Challenges in Maintaining Layout Hierarchy
5.2.3 Pros and Cons of Maintaining Hierarchy in Migration
5.3 The S-o-C Mixing and Matching in Retargeting
5.4 Designing VLSI Chips for Ease of Reuse
5.4.1 Some Guidelines to Facilitate Hard IP Migration
6 SOLUTIONS NEEDED FOR RETARGETING AND LAYOUT OPTIMIZATION
6.1 The Postlayout Optimization Process
6.1.1 The Theoretically Ideal Optimization Approach
6.2 IP Reuse Through Retargeting
6.2.1 A Traditional, Robust, Retargeting Product
6.2.2 State-of-the-art, Fully Hierarchical Retargeting
6.3 Tools for High Productivity IP Creation on the Layout Level
6.4 Optimization of Physical Layout for Performance &Better Yield
6.4.1 Optimizing Transistor Sizes
6.4.2 Interconnect Layout Adjustments
6.4.3 Yield Enhancements With XTREME
7 SOME GENERAL OBSERVATIONS
7.1 Some Reasons for Looking at Both Hard IP and Soft IP Reuse
7.2 Design Flows: A Visual Perception of Design Efforts
7.2.1 Considerations When Looking at Design Flows
7.2.2 A Pre-DSM Design Flow
7.2.3 A DSM Design Flow
7.2.4 4 Hard IP Reuse Flow
7.3 Examining Flows: Design from Scratch, Soft IP and Hard IP Reuse
7.3.1 Design from Scratch
7.3.2 Soft IP Reuse
7.3.3 Hard IP Reuse
7.4 Summarizing Remarks
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