Hard IP, an introduction
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Looking at Figures 3.2 and 3.3, we will now discuss how one can determine the capacitances associated with connectors in such an arrangement. We will focus only on parasitic capacitances for now. The resistance part of the interconnect will be determined easily later, although in the end finding the model to be used for the delay analysis is not that straightforward, because of the distributed character of the interconnects. Fortunately, years of timing analysis research on VLSI chips have led to elegant ways to deal with this problem, as we shall see a bit later [6].

The problem of determining the parasitic capacitances surrounding conductors is an electrostatic field problem. It is based 011 the same simple principles as Coulomb's law. For anybody with a good understanding of electromagnetic field theory, a look at the cross-sectional view in Figure 3.3 will make it apparent that it is not difficult to conceptually understand these parasitic capacitances. However, solving the mathematical problem of determining their values for a large range of geometrical layout dimensions is quite difficult and computationally demanding.

Figure 3.3 shows an illustration of most of the capacitance components surrounding a particular interconnect and the interconnects are held in place by the oxide (the dielectric) surrounding. The oxide only changes (unfortunately increases) the degree of electrical coupling capacitance between interconnects, because the permittivity is greater than one. For an oxide that is uniform, this does not distort the field distribution.

For an analysis of time delays and coupling affecting signal integrity, we must focus on the dominant capacitive effects to simplify the analysis as a much as is consistent with the desired accuracy. In Figure 3.4, we show an interconnect with the capacitive effects of only its nearest neighbors. This is generally sufficient for both the time delay and coupling analyses.

Figure 3.4 shows all the critical physical effects. It shows:

  • The capacitance directly under the conductor to the substrate.
  • The capacitance due to fringing effects contributing capacitance from the side walls of the interconnect to the substrate but not coupling with the adjacent interconnects.
  • The coupling capacitances to adjacent interconnects.
  • Crossover capacitances to different layers.
  • Shielding effects that lower capacitance values.

Fig. 3.4 A Realistic Model for Determining the Important Parasitics

Coupling capacitances beyond the nearest neighbor interconnects are not shown to simplify the picture at least somewhat and because the shielding effects greatly lower their significance.

Finally, to start to “develop a feel” for the geometrical dependency of some of the major capacitive components of interconnects, Figure 3.5 shows a simpler but clearly pertinent geometrical structure for which there are exact solutions [11]. The theoretical basis for understanding the curves in Figure 3.5 are presented in the next section.

Fig. 3.5 Exact Values for Parasitic Capacitances for a “Simpler" Structure

Clearly the partitioning of the capacitances in Figure 3.5 is not as sophisticated as was shown in Figure 3.4. It is a simplification of what needs to be determined for DSM technologies but it was published in 1975 as just an aside. In addition, because it is published data and focuses primarily on showing basic ideas, it can be openly discussed, while most such data based on current DSM geometries is proprietary information.

The data in Figure 3.5 is an accurate solution and it beautifully shows how at least some of the capacitive components illustrated in Figures 3.4 and 3.5 change as a function of one of the important parameters, the spacing (S) between interconnects. The focus of the discussions here is to show the basic ideas of how useful data for the eventual layout optimization of a VLSI chip can be generated. This is not to come up with exact results, which are different in every case anyway. The goal is to show and understand some of the assumptions and limitations made to determine DSM parasitic parameters, as well as to show the advantage of knowing how to “play” with the trade-offs.

The curves in Figure 3.5 show certain capacitance values as a function of interconnect spacings. Every point on these curves has been generated with extensive numerical calculations. Clearly, we can not invoke a process of numerical solutions for the partial differential equations and integral equations that are the basis for the results in Figure 3.5 for an optimization algorithm using compaction. Instead, we need to find the simplest possible analytical expressions that are sufficiently accurate for describing these curves with a curve-fitting process. Such an analytical expression can then be used by a compaction engine.

Because we can vary the interconnect spacing and simultaneously the width of the interconnects, we need slightly more sophisticated curves. We need curves that also contain the effects due to interconnect width variations. Such curves as well as analytical expressions to fit these curves are generally part of chip-making companies' know-how. In the next section, we discuss in more detail how to obtain such curves and comment on some of the published results on the subject.

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