Hard IP, an introduction
  « Previous TopNext »  

In Chapter 1, we discuss three topics:

  1. We start by discussing some of the major challenges in DSM VLSI chip design and how pre-DSM design practices need to adjust to the new reality of DSM technologies.
  2. We then present some ideas on how Hard IP will help to address issues such as how to achieve a more predictable time-to-market, how to prolong benefits from previous investments in the design of complex chips by reusing them, and how to lower the risks of not filling processing lines while being able to absorb last minute processing tweaking in a design for larger yield and better performance.
  3. Finally, we preview the potential solutions proposed in this book that are discussed in more detail in the following chapters.

Throughout the discussions in Chapter 1, we make statements based on the assumption that IP reuse will actually help address some of the problems faced by the chip design and manufacturing industries. Although this is consistent with what is generally expected when talking about IP reuse and it helps to initiate a discussion of the issues, we will need to justify these statements as we move through the chapters.


Keeping in mind the need for improvements in design productivity, we will look at the steps involved in designing today's complex DSM VLSI chips versus the much discussed IP reuse methodologies. It seems appropriate to examine and compare the effort, time, skill level, tools and risks involved in designing chips from scratch versus Soft or Hard IP reuse.

The generally accepted standard for growth in complexity of VLSI chips has been set by Gordon Moore's Law. It seems that, at least for now, the capabilities of manufacturing chips have no problem following this law. However, design productivity has difficulty keeping up with manufacturing progress. All efforts to achieve a higher level of design intent and the increasing use of behavioral-level synthesis are still not sufficient to prevent mounting difficulties in providing new VLSI chip designs fast enough to keep processing lines filled with fresh, innovative designs, ones that take full advantage of manufacturing capabilities. Meeting the challenges of designing multimillion transistor chips, the level of complexity that can currently be fabricated, requires radically different approaches to design. And once again we hear the well worn battle cry, “We need a paradigm shift!” This shift could be referred to as Intellectual Property reuse (IP reuse).

This need for a substantial increase in design productivity triggered the inconceivable in today's “newly improved driven” world, i.e. to reuse existing designs and retarget them to the latest, most advanced processes. Of course, the only part that would literally be reused is the design content, which is in fact a reuse of IP content.

While retargeting a chip, additional performance improvements could at the same time be achieved with layout optimization. For now, we will only discuss simple retargeting by taking advantage of the tighter, higher performance process layout rules. The other step alluded to here, performance optimization through small adjustments brought about by pushing polygons around, is discussed in Chapter 3.

As already indicated, we discuss in this chapter both Soft and Hard IP, but the Soft IP discussion will be largely limited to a comparison of the two methodologies and pointing out complementary values of Soft and Plard IP. After all, Soft IP reuse is well established and requires no explanation. On the other hand, Hard IP reuse using compaction is a less common approach that has yet to be fully accepted by the engineering community. This should not be surprising.

Polygon-based Hard IP retargeting of large blocks, with limited hierarchy maintenance, has only recently become technologically feasible, and full hierarchy maintenance is just around the corner. In fact, many experts in the hi-tech industry still do not believe in its feasibility, in spite of what is now a proven track record established by successful chip-based projects. But different approaches are not always quickly accepted. Even in Silicon Valley, the “Paradise for new ideas,” many new methodologies are embraced more slowdy than hoped for, because solutions that work are already in place. Proven technologies are not easily displaced. Nevertheless, in general, new ideas will eventually be accepted, combined with a little perseverance.

For reuse of existing iP, there are at least two paths that have been followed. As is usually the case, each is being proclaimed as “the only way to go.” One approach is Soft IP reuse, the other Hard TP reuse. We will show later that in some cases they are actually complementary. For now, we will discuss Soft IP and Hard IP reuse as standalone processes.

For Soft IP reuse, existing high-level software chip descriptions can be targeted to newer processes for Soft IP reuse. Much, if not most, of the high-level programming could be reused: test scripts, simulation scripts, models.

For Hard IP reuse, existing layout databases will be transformed according to new physical layout design rules. As we already know, the methodology is based on compaction. We will show that for Hard IP reuse, existing simulation and test vector suites can be reused and any software, such as control programs developed lor the part in question, can also be reused.

As mentioned, such retargeted Plard IP will then yield a higher performance, and be denser and consequently smaller than in the original layout. In addition, several of these retargeted designs, can now be combined in one chip as a S-o-C approach, providing much higher levels of integration than was previously possible. This retargeting of proven designs to newer technologies has become one of the more promising approaches to achieving the needed gains in productivity.

It seems obvious that a reuse of existing, proven designs by retargeting to more advanced technologies, as opposed to starting from scratch, should lead to substantial savings in engineering and a reduction of risks, while taking full advantage of advancements in processing technologies. By shortening the cycle time required to produce a “new” chip, it would also address the hottest issue at present in the market: A shortening of the time-to-market. The main goal is to benefit from the rapid advances in processing technology, combined with reuse of knowledge previously invested in these chips.

  « Previous TopNext »  
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy