Bit-Slice Design: Controllers and ALUs

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White



Table of Contents

1. Introduction

2. Simple Controllers

3. Adding Programming Support to the Controller

4. Refining the CCU

5. Evolution of the ALU

6. The ALU and Basic Arithmetic

7. Tying the System Together




Simple Controller continued

Last Edit October 10, 1996; May 1, 1999; July 9, 2001

Unconditional Branch

Often microroutines may start differently but end with the same steps. Also, once starting addresses are mapped (and the microinstruction position in memory fixed), it might be found that a microroutine needs to be extended in length. For these and other cases, the existence of a GO TO or unconditional branch next-address control is desireable. The instruction flow is shown in Figure 2-8. This instruction causes the counter to be loaded with the desired next address, which is not in sequence with the current address. This is not a start address; therefore, the map is not involved. Instead, the microword width must be expanded as shown in Figure 2-9 to contain a branch address field, up to n bits wide, and a next-address-select field. The map and the branch address lines would be input to a 2:1 MUX network, n bits wide, with the MUX select operated by the address selection field of the microword. The MUX outputs are the inputs to the counter, as shown in Figure 2-10.

Figure 2-8 Flow Diagram of Unconditional Jump - the GOTO statement (JMP, jump)

diagram of a JMP sequence

Figure 2-9 Expanded Microword.
Width of the microword increases with increased flexibility and control.

Load, EN
Op Code
o o o
1 bit 1 bit n bits 4-6 bits 2 bits 1 bit 1-4 bits 1-4 bits

Figure 2-10 CCU With Branch Capability

simple block diagram with an address select MUX added between mapping PROM and counter and expanded microword to carry address select and branch to address

A sample piece of microcode, shown in Figure 2-11, highlights the load control to the counter, the address MUX select, and the branch address field. Assume that the program start address is at address 50. Execution is then seen to be sequential until address 53, which loads the counter (LDCTL=1) with a branch address (ADR MUX=0) supplied at address 53 (BR ADR=90). The next microinstruction executed is located at address 90. Address 90 causes a branch back to address 13. Address 14 causes the counter to be loaded (LDCTL=1) with a new start address (ADR MUX=1). This is the last step in the microroutine that began at address 50.

Figure 2-11 Microcode, Demonstrating the Use of Jumps. (X bits are "don't care" for this op code; numbered bits are address for this op code.)

microcode written to show unconditional JMP  sequences

The width of the branch address field, B, could be less than n, restructing the allowable range of the branch (for example, by leaving the n - B high-order bits unchanged). This complicates the task for the microprogrammer and should be avoided by beginning designers. Good programming practices require that the various parts of the microroutines be kept in a relatively compact area, if possible, without artificial enforcement.


For information about this file or to report problems in its use email

Copyright © September 1996, 1999, 2001, 2002 Donnamaie E. White White Enterprises

S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy