Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White


Faults and Fault Detection

Last Edit July 22, 2001


In any circuit composed of logic gates there is the possibility of the occurrence of a fault. A fault is defined to have occurred when any circuit output variable assumes a value of 1, 0 or X that differs from the value expected. When this occurs, the circuit violates the original circuit equations.

Fault detection requires that a vector test set provide a test to detect when any fault has occurred in a circuit path. Fault location requires that sufficient tests be included such that the specific node in failure can be located. In general, fault location requires a larger vector set.


A circuit is judged on the ease and ability of the input variables to set internal and output variables to specific values. This is defined as circuit controllability. The ideal case is when internal variables can be set with one input vector (input variable configuration). The worst cases require that multiple vectors be gated through the circuit until a target internal node is set or forced to a desired value.


A circuit is judged on the ease and ability to propagate the values on input and internal variables to a primary and therefore observable output. This is defined as circuit observability. The best case is when an internal variable propagates directly to an observable output within the vector time step. The worst cases require that multiple vectors be gated through the circuit until a target internal node has propagated to an observable output. In extreme cases, a fault may be undetectable.

Masking a Fault

The presence of an internal or input fault may not be observable at any circuit output. In this case the fault is considered to be masked. A single fault may be masked as the result of the causes shown in Table 9-1.

Masked faults are undetectable by definition since the observed circuit behavior is correct.

The occurrence of a second fault may uncover a previously undetectable fault. To be complete, a vector test set must include tests for this case.

Table 9-1 Single Fault Masking

  • reconvergent fan-out where unequal parity changes have occurred
  • circuit redundancy, deliberate or otherwise
  • previous occurrence of an undetectable fault




Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com

S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy